EE45700 Design/Simulation Assignment
EE45700 Design/Simulation Assignment
EE45700 Design/Simulation Assignment
8-bit parallel to serial converter
• This assignment is due on 5/10/22
• Use LTSpice
• Use logisim (http://www.cburch.com/logisim/) to verify your logic design before circuit level implementation
• Show your hand analysis for the design (typed)
• Everything must be typed
• Use IEEE journal format (located here)
• Must label figures as well as equations used
• The report consists of: Introduction, design methodology (justification for topologies used), analysis, simulation results
and conclusion.
• Use the 0.35um transistors provided in the ee457_035.lib
Design an 8-bit parallel to serial converter with complementary serial outputs as seen in figure 1. The circuit is
composed of three stages, the logic, the shift register and the buffer output.
The device works as follows (refer to figure 1):
1. When the parallel-load input PL is LOW, parallel data from the inputs D0 to D7 are loaded into the
register asynchronously.
2. When PL is HIGH, data enters the register serially at the input DS. It shifts one place to the right
(Q0Q1Q2, etc) with each positive-going clock transition.
3. The inputs have schmitt triggers which makes them tolerant for slower input rise and fall times
Figure 1: 8-bit parallel to serial converter Functional Block diagramTable 1: Function Table
Table 2: Pin Description
EE45700 Design/Simulation Assignment
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